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(parent: e26fbf7) | patch
[IA64] Fix wrong insertion of TLB entry in region 0
authorAlex Williamson <alex.williamson@hp.com>
Mon, 1 Oct 2007 15:57:50 +0000 (09:57 -0600)
committerAlex Williamson <alex.williamson@hp.com>
Mon, 1 Oct 2007 15:57:50 +0000 (09:57 -0600)
commitf529f8d46b4381cb5969ccd1701234b8993b07ad
tree521dfc86f6e4c648f90e8139cdd9851532677f6ftree | snapshot
parente26fbf7c55cc1d14313144d666bb50d662099df0commit | diff
[IA64] Fix wrong insertion of TLB entry in region 0

On PV domain with metaphysical mode, emulation of itc.d in region 0
doesn't work well and inserts an wrong TC entry.
Because set_one_rr() doesn't set the machine region register.
i.e. metaphyisical_rr0 is used instead of guest's rr[0].

This bug causes Dom0/U crash when an application uses region 0.
Actually I met the crash when I was building open GFW (java uses
region 0).

Signed-off-by: Kouya Shimura <kouya@jp.fujitsu.com>
xen/arch/ia64/xen/regionreg.c diff | blob | history
xen/arch/ia64/xen/vcpu.c diff | blob | history
xen/include/asm-ia64/regionreg.h diff | blob | history
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